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  rev.1.00, jun.14.2004, page 1 of 8 BB505M build in biasing circuit mos fet ic uhf rf amplifier rej03g0365-0100z rev.1.00 jun.14.2004 features ? build in biasing circu it; to reduce using parts cost & pc board space. ? low noise; nf = 1.5 db typ. at f = 900 mhz ? high gain; pg = 24 db typ. at f = 900 mhz ? withstanding to esd; build in esd absorbing diode. withstand up to 190 v at c = 200 pf, rs = 0 conditions. ? provide mini mold packages; mpak-4 (sot-143mod) outline mpak-4 1 4 3 2 1. source 2. gate1 3. gate2 4. drain notes: 1. marking is ?es-?. 2. BB505M is individual type number of renesas bbfet. absolute maximum ratings (ta = 25c) item symbol ratings unit drain to source voltage v ds 6v gate1 to source voltage v g1s +6 ?0 v gate2 to source voltage v g2s +6 ?0 v drain current i d 20 ma channel power dissipation pch note3 300 mw channel temperature tch 150 c storage temperature tstg ?55 to +150 c notes: 3. value on the glass epoxy board (50 mm 40 mm 1 mm ).
BB505M rev.1.00, jun.14.2004, page 2 of 8 electrical characteristics (ta = 25c) item symbol min typ max unit test conditions drain to source breakdown voltage v (br)dss 6??vi d = 200 a, v g1s = v g2s = 0 gate1 to source breakdown voltage v (br)g1ss +6 ? ? v i g1 = +10 a, v g2s = v ds = 0 gate2 to source breakdown voltage v (br)g2ss +6 ? ? v i g2 = +10 a, v g1s = v ds = 0 gate1 to source cutoff current i g1ss ? ? +100 na v g1s = +5 v, v g2s = v ds = 0 gate2 to source cutoff current i g2ss ? ? +100 na v g2s = +5 v, v g1s = v ds = 0 gate1 to source cutoff voltage v g1s(off) 0.5 0.7 1.0 v v ds = 5 v, v g2s = 4 v, i d = 100 a gate2 to source cutoff voltage v g2s(off) 0.5 0.7 1.0 v v ds = 5 v, v g1s = 5 v, i d = 100 a drain current i d(op) 71115ma v ds = 5 v, v g1 = 5 v, v g2s = 4 v r g = 220 k ? forward transfer admittance |y fs |283338ms v ds = 5 v, v g1 = 5 v, v g2s = 4 v r g = 220 k ? , f = 1 khz input capacitance c iss 1.4 1.75 2.1 pf output capacitance c oss 1.0 1.4 1.8 pf reverse transfer capacitance c rss ? 0.03 0.05 pf v ds = 5 v, v g1 = 5 v, v g2s = 4 v r g = 220 k ?, f = 1 mhz power gain pg 19 24 29 db noise figure nf ? 1.5 2.2 db v ds = 5 v, v g1 = 5 v, v g2s = 4 v r g = 220 k ?, f = 900 mhz bias circuit for operating items (i d(op) , |y fs |, ciss, coss, crss, nf, pg) gate 1 source drain gate 2 r g a i d v g2 v g1
BB505M rev.1.00, jun.14.2004, page 3 of 8 900 mhz power gain, noi se figure test circuit input ( 50 ? ) output ( 50 ? ) c2 c1 l1 l2 l3 l4 s g1 g2 r1 r2 c3 r3 rfc c6 c5 c4 d v g2 v g1 v d c1, c2 c3 c4 to c6 r1 r2 r3 variable capacitor (10 pf max) disk capacitor (1000 pf) air capacitor (1000 pf) 220 k ? 47 k ? 4.7 k ? : : : : : : 26 3 3 l2: 18 10 10 l4: 29 7 7 l3: ( 1mm copper wire) unit : mm rfc : 1mm copper wire with enamel 4 turns inside dia 6 mm 21 10 8 l1: 10
BB505M rev.1.00, jun.14.2004, page 4 of 8 main characteristics drain to source voltage v ds (v) drain current i d (ma) typical output characteristics gate1 voltage v g1 (v) drain current i d (ma) drain current vs. gate1 voltage gate1 voltage v g1 (v) forward transfer admittance |y fs | (ms) forward transfer admittance vs. gate1 voltage channel power dissipation pch * (mw) maximum channel power dissipation curve ambient temperature t a ( c) * value on the glass epoxy board (50mm 40mm 1mm) gate resistance r g (k ? ) drain current i d (ma) drain current vs. gate resistance gate2 to source voltage v g2s (v) input capacitance ciss (pf) input capacitance vs. gate2 to source voltage 400 300 200 100 0 50 100 150 200 0 1 2345 v ds = 5 v r g = 220 k ? 2 v v g2s = 1 v 20 15 10 5 3 v 4 v 0 100 200 500 1000 v ds = 5 v v g1 = 5 v v g2s = 4 v 5 10 15 20 0 1 2345 20 v g2s = 4 v v g1 = v ds r g = 120 k ? 150 k ? 180 k ? 220 k ? 270 k ? 330 k ? 15 10 5 50 40 30 20 10 0 12345 v g2s = 1 v 4 v 3 v 2 v v ds = 5 v v g1 = 5v r g = 220 k ? f = 1 khz 0 1 2 34 4 3 2 1 0 v ds = 5 v v g1 = 5 v r g = 220 k ? f = 1 mhz
BB505M rev.1.00, jun.14.2004, page 5 of 8 noise figure nf (db) noise figure vs. gate resistance gate2 to source voltage v g2s (v) power gain vs. gate2 to source voltage noise figure vs. gate2 to source voltage power gain pg (db) power gain vs. gate resistance gate resistance r g (k ? ) 0 100 200 500 1000 v ds = 5 v v g1 = 5 v v g2s = 4 v f = 900 mhz 50 40 30 20 10 power gain pg (db) 25 20 15 10 5 0 1234 v ds = 5 v v g1 = 5 v r g = 220 k ? f = 900 mhz gain reduction gr (db) 0 1234 10 20 30 40 v ds = 5 v v g1 = 5 v r g = 220 k ? f = 900mhz noise figure nf (db) gate2 to source voltage v g2s (v) 0 4 3 2 1 100 200 500 1000 v ds = 5 v v g1 = 5 v v g2s = 4 v f = 900 mhz 5 4 3 2 1 1 2 34 0 v ds = 5 v v g1 = 5 v r g = 220 k ? f = 900 mhz gate resistance r g (k ? ) gain reduction vs. gate2 to source voltage gate2 to source voltage v g2s (v)
BB505M rev.1.00, jun.14.2004, page 6 of 8 10 5 4 3 2 1.5 1 .8 -2 -3 -4 -5 -10 .6 .4 .2 0 -.2 -.4 -.6 -.8 -1 -1.5 .2 .4 .6 .8 1 2 3 4 5 1.5 10 0 30 60 90 120 150 180 -150 -90 -60 -30 -120 30 60 90 120 150 180 -150 -90 -60 -30 -120 10 5 4 3 2 1.5 1 .8 -2 -3 -4 -5 -10 .6 .4 .2 0 -.2 -.4 -.6 -.8 -1 -1.5 .2 .4 .6 .8 1 2 3 4 5 1.5 10 scale: 1 / div. scale: 0.02 / div. 0 condition: v ds = 5 v, v g1 = 5 v, v g2s = 4 v r g = 220 k ? , zo = 50 ? 50 to 1000 mhz (50 mhz step) condition: v ds = 5 v, v g1 = 5 v, v g2s = 4 v r g = 220 k ? , zo = 50 ? 50 to 1000 mhz (50 mhz step) condition: v ds = 5 v, v g1 = 5 v, v g2s = 4 v r g = 220 k ? , zo = 50 ? 50 to 1000 mhz (50 mhz step) condition: v ds = 5 v, v g1 = 5 v, v g2s = 4 v r g = 220 k ? , zo = 50 ? 50 to 1000 mhz (50 mhz step) s 11 parameter vs. frequency s 21 parameter vs. frequency s 12 parameter vs. frequency s 22 parameter vs. frequency
BB505M rev.1.00, jun.14.2004, page 7 of 8 s parameter (v ds = 5 v, v g1 = 5 v, v g2s = 4 v, r g = 200 k ? , z o = 50 ? ) s11 s21 s12 s22 f (mhz) mag ang mag ang mag ang mag ang 50 0.991 -2.4 3.55 178.2 0 .009 -64.5 0.976 -1.8 100 0.991 -5.9 3.58 172.9 0 .011 18.0 0.995 -3.1 150 0.993 -8.9 3.58 170.2 0 .002 61.4 0.990 -5.2 200 0.983 -11.9 3.56 165. 9 0.004 77.7 0.986 -6.5 250 0.977 -15.3 3.59 162. 6 0.006 87.6 0.986 -8.2 300 0.969 -18.5 3.50 155.5 0 .008 87.8 0.990 -12.9 350 0.962 -21.6 3.51 151.0 0 .006 94.6 0.984 -15.1 400 0.952 -25.2 3.52 146.9 0 .007 80.9 0.982 -17.3 450 0.944 -28.7 3.52 142.6 0 .008 87.1 0.977 -19.5 500 0.929 -32.2 3.51 138.2 0 .008 78.1 0.973 -21.8 550 0.914 -36.0 3.51 133.4 0 .008 74.7 0.968 -24.0 600 0.897 -40.0 3.50 129.0 0 .008 84.8 0.963 -26.1 650 0.881 -44.2 3.49 124.2 0 .010 72.6 0.957 -28.2 700 0.863 -48.3 3.47 119.4 0 .010 67.5 0.950 -30.4 750 0.842 -52.7 3.45 114.5 0 .008 78.7 0.943 -32.6 800 0.819 -57.3 3.41 109.7 0 .008 82.1 0.939 -34.6 850 0.797 -62.0 3.37 104.9 0 .008 85.3 0.931 -36.6 900 0.775 -66.8 3.33 99.9 0 .008 95.6 0.924 -38.7 950 0.746 -71.8 3.27 94.9 0 .007 97.4 0.916 -40.6 1000 0.721 -76.9 3.20 90. 2 0.007 122.8 0.909 -42.4
BB505M rev.1.00, jun.14.2004, page 8 of 8 package dimensions 0.16 0 ? 0.1 + 0.1 ? 0.06 0.95 0.85 1.8 0.2 0.65 1.5 0.15 0.65 1.1 + 0.2 ? 0.1 0.95 0.95 1.9 0.2 2.95 0.2 0.4 + 0.1 ? 0.05 0.6 + 0.1 ? 0.05 2.8 + 0.2 ? 0.6 0.3 0.4 + 0.1 ? 0.05 package code jedec jeita mass (reference value) mpak-4 ? conforms 0.013 g 0.4 + 0.1 ? 0.05 as of january, 2003 unit: mm ordering information part name quantity shipping container BB505Mes- 3000 taping note: for some grades, production may be terminated. please contact the renesas sales office to check the state of production before ordering the product.
keep safety first in your circuit designs! 1. renesas technology corp. puts the maximum effort into making semiconductor products better and more reliable, but there is a lways the possibility that trouble may occur with them. trouble with semiconductors may lead to personal injury, fire or property damage. remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placeme nt of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. notes regarding these materials 1. these materials are intended as a reference to assist our customers in the selection of the renesas technology corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to renesas t echnology corp. or a third party. 2. renesas technology corp. assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. all information contained in these materials, including product data, diagrams, charts, programs and algorithms represents i nformation on products at the time of publication of these materials, and are subject to change by renesas technology corp. without notice due to product improvement s or other reasons. it is therefore recommended that customers contact renesas technology corp. or an authorized renesas technology corp. product distrib utor for the latest product information before purchasing a product listed herein. the information described here may contain technical inaccuracies or typographical errors. renesas technology corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies o r errors. please also pay attention to information published by renesas technology corp. by various means, including the renesas techn ology corp. semiconductor home page (http://www.renesas.com). 4. when using any or all of the information contained in these materials, including product data, diagrams, charts, programs, a nd algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. renesas technology corp. assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. renesas technology corp. semiconductors are not designed or manufactured for use in a device or system that is used under ci rcumstances in which human life is potentially at stake. please contact renesas technology corp. or an authorized renesas technology corp. product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerosp ace, nuclear, or undersea repeater use. 6. the prior written approval of renesas technology corp. is necessary to reprint or reproduce in whole or in part these materi als. 7. if these products or technologies are subject to the japanese export control restrictions, they must be exported under a lic ense from the japanese government and cannot be imported into a country other than the approved destination. any diversion or reexport contrary to the export control laws and regulations of japan and/or the country of destination is prohibited. 8. please contact renesas technology corp. for further details on these materials or the products contained therein. sales strategic planning div. nippon bldg., 2-6-2, ohte-machi, chiyoda-ku, tokyo 100-0004, japan http://www.renesas.co m renesas technology america, inc. 450 holger way, san jose, ca 95134-1368, u.s.a tel: <1> (408) 382-7500 fax: <1> (408) 382-7501 renesas technology europe limited. dukes meadow, millboard road, bourne end, buckinghamshire, sl8 5fh, united kingdom tel: <44> (1628) 585 100, fax: <44> (1628) 585 900 renesas technology europe gmbh dornacher str. 3, d-85622 feldkirchen, germany tel: <49> (89) 380 70 0, fax: <49> (89) 929 30 11 renesas technology hong kong ltd. 7/f., north tower, world finance centre, harbour city, canton road, hong kong tel: <852> 2265-6688, fax: <852> 2375-6836 renesas technology taiwan co., ltd. fl 10, #99, fu-hsing n. rd., taipei, taiwan tel: <886> (2) 2715-2888, fax: <886> (2) 2713-2999 renesas technology (shanghai) co., ltd. 26/f., ruijin building, no.205 maoming road (s), shanghai 200020, china tel: <86> (21) 6472-1001, fax: <86> (21) 6415-2952 renesas technology singapore pte. ltd. 1, harbour front avenue, #06-10, keppel bay tower, singapore 098632 tel: <65> 6213-0200, fax: <65> 6278-8001 renesas sales offices ? 2004. renesas technology corp., all rights reserved. printed in japan. c olophon .1 .0


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